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SWIFT
SWIFTsim
Commits
9d6f91e7
Commit
9d6f91e7
authored
Nov 27, 2018
by
Peter W. Draper
Browse files
Silly dangling brace...
parent
0d257112
Changes
1
Hide whitespace changes
Inline
Side-by-side
src/engine.c
View file @
9d6f91e7
...
...
@@ -1105,7 +1105,7 @@ void engine_repartition_trigger(struct engine *e) {
(
maxtime
-
mintime
)
/
mean
,
abs_trigger
);
e
->
forcerepart
=
1
;
}
else
{
if
(
e
->
verbose
)
{
if
(
e
->
verbose
)
message
(
"trigger fraction %.3f =< %.3f will not repartition"
,
(
maxtime
-
mintime
)
/
mean
,
abs_trigger
);
}
...
...
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